ctc0 and cfc0

[phobox]

what do those opcodes do?

the very first instruction executed by the psp when turned on is

0xBFC00000: 0x40C22000 '. .@' - ctc0 $v0, $4

what does it mean?
any help is appreciated

[sauron_le_noir]

CTC0 is a COP0 control register

COP0:
MFC0(010000:00000:rt:c0dr:00000:000000)
CFC0(010000:00010:rt:c0cr:00000:000000)
MTC0(010000:00100:rt:c0dr:00000:000000)
CTC0(010000:00110:rt:c0cr:00000:000000)

look at : http://www.gp32x.com/board/index.php?/t ... ntry720831

ask hlide

[phobox]

Well does it mean that it copies value from general purpose register $v0 to CP0 control register $4?

but.. since this is the very first instruction executed... what value is contained in $v0??


and then.. what is the meaning of control register $4? where can i find a list of all functions?

[hlide]

when calling an interrupt/exception handler, psp uses to save $v0 and $v1 into COP0 $4 and $5(not sure for it) so the handler can use $v0 and $v1 for temporary need. At the end of the handler, it restores original values of $v0 and $v1 through those both COP0 registers.

Normally MIPS uses $k0 and $k1 for this purpose. But psp firmware choses to use them for another purpose.

[m0skit0]

And what's the purpose of $k0 and $k1 on PSP firmware if I may ask?

[phobox]

thanks for the info,
but

ctc0 $v0 $4 means copy data FROM $v0 to $4 right?, but this is the first instruction executed by the psp (the first instruction of the preipl).. how is it possible to copy v0 to $4? what is it stored in v0?

is the $4 the register that in standard MIPS R4000 processor is used for the TLB ? (which is not implemented in Allegrex)

[hlide]

@m0skit0:

$k0 and $k1 : kernel registers - those registers used to be reserved by the an OS as temporary save/restore registers in a interrupt/exception handler. PSP firmware uses them for another purpose : $k0, something like KTLS probably (not sure about it as i don't care about) and $k1 to contain special flags for access protection when calling a kernel firmware function.

@phobox:
don't be confused : ctc0 is not mtc0, both don't use the same COP0 register set. cfc0/ctc0 is for moving from/to one register of the second COP0 registers set. Those registers are specifical to PSP indeed. Whereas the first set (through mfc0/mtc0) is almost compatible with the standard MIPS R4000 COP0. One point : there is no MMU, i.e, no TLB in Allegrex (PSP processor) so those TBL registers you're refering are not implemented.

[hlide]

but this is the first instruction executed by the psp (the first instruction of the preipl).. how is it possible to copy v0 to $4? what is it stored in v0?

ok, you don't know how the hardware of a processor runs.

When resetting, you call a interrupt handler. Under a very specific condition, when setting a special bit, you can initiate this preipl handler (it's just an interrupt). I guess the programmer codes it as a generic handler : you need to save some registers before running an asynchronous code then restore them at the end. In psp firmware, they choose to save register $v0 and $v1 (instead using $k0 and$k1) into two special COP0 registers so they can use $v0 and $v1 as temporary registers in the handler. At the end of your generic interrupt handler, you must restore the original $v0 and $v1.

You don't understand ? ok, let's consider an hardware timer : you configure a period so the timer will issue a call to the timer interrupt handler. As it can occur at any place of your running code, you cannot let the interrupts to scratch the registers. But the issue is the handler also needs some temporary registers to execute its tasks so you need to save some registers and then restore them at the end so it can retrieve the original values in the registers when resuming the interrupted code.

[m0skit0]

I knew what the MIPS standard said about it, but not what PSP firmware used them for. Thanks for info.

[hlide]

I knew what the MIPS standard said about it, but not what PSP firmware used them for. Thanks for info.

yeah, i realised too late. But let's say it might be instructive for other people ;).