Boot Code

[zilmar]

Hi

I am created a dump of the boot code, I am presuming that it has not been changed once the system starts (0xBFC00000 to 0xBFC10000). I am just trying to understand what it is doing.

BFC00000: ctc0 v0, 6
BFC00004: mfc0 v0, Unknown 22
BFC00008: bnez v0, BFC00040
BFC0000C: nop
BFC00010: cfc0 v0, 9
BFC00014: jr v0
BFC00018: nop

I did not think that COP 0 had any control registers? also unsure what cop0 reg 22 is, any clues where I should look for this info ?

[ryoko_no_usagi]

Hi

I am created a dump of the boot code, I am presuming that it has not been changed once the system starts (0xBFC00000 to 0xBFC10000). I am just trying to understand what it is doing.

BFC00000: ctc0 v0, 6
BFC00004: mfc0 v0, Unknown 22
BFC00008: bnez v0, BFC00040
BFC0000C: nop
BFC00010: cfc0 v0, 9
BFC00014: jr v0
BFC00018: nop

I did not think that COP 0 had any control registers? also unsure what cop0 reg 22 is, any clues where I should look for this info ?

Cop0 is a custom effort by Sony; apparently it has control registers. Reg22 indicates whether main or ME core (0 = main, 1 = ME). Groepaz/Hitmen released a hardware doc with some info on cop0.

[zilmar]

Thanks I think I found the doc you meant at
http://psp3d.com/showthread.php?t=3709

[chrismulhearn]

The r4000 manual lists CP0 $22 as "reserved". The PSP hardware doc lists it as "Virtual Address of Exception Vector."

It also lists CP0 $6 as "Number of Wired TLB entries". This controls how many TLB entries are unchangable. this register is not included in the PSP hardware document.

By loading "0" in there , they are saying "no TLB entries are fixed".

In all likelihood though, this is a case where the Allegrex and the R4000 differ. I've heard numerous places that the CP0 in Allegrex is different from the R4000s, (The only thing I've verified for myself is that the interrupt control in the CP0 status register is the same in both r4000 and allegrex) I'd love to know how people found out the Allegrex CP0 is different??? Is that just speculation or has it been verified? And if there is no TLB support, why does the PSP hardware doc list CP0 $22 as "_VIRTUAL_ address of exception vector" ?

confusing.......

-Chris

[chrismulhearn]

Actually, I was thinking those were all "mfc0" and "mtc0" instructions.

But for CP0 registers "6" and "9", its actually using the "cfc0" and "ctc0" instructions.

For the uninitiated, the r4000 manual states that "CFCz" and "CTCz" move data from Coprocessor(z)'s *control* registers (as opposed to its *general* registers accessible via mfc and mtc instructions.)

Note that the r4000 manual ALSO states that CFCz and CTCz are *not valid* for cp0, probably because it has no control registers.

But apparantly Allegrex's CP0 does! shucks!!

Does anyone have any more info about this CP0 than what is in the PSP hardware doc?