IronPeter wrote:d-range, any nontrivial push buffers.
So you must memset( 0 ) fifo buffer, make lv1_gpu_context_attribute call, dump fifo bufer ( if there are any non zero values ). Any nonzero values are interesting for me.
Push buffer after FB_SETUP in ps3fb.c is the first candidate to investigate.
PS. FW 2.01 is not very interesting. FW 2.10 is.
IronPeter, i have my custom YDL 2.6.16 firmware modified with 20MB of XRAM and the FIFO Buffer with 2MB of size.
Now, it work (before, it fail because the 64KB of FIFO size as i say to you in my PM).
I have dumped this area yesterday:
http://mods.elotrolado.net/~hermes/ps3/fifo.zip
This fifo dump is obtained after of the enter_direct() function, without the "init_ramin" code
ctrl[0x10]==ctrl[0x11]== 0xe201448 (fifo offset is 18MB in my case: 18 MB of XRAM and after, 2 MB of FIFO area)
I can see as you can alloc 254 MB of DDR Maximum (the wiki say 252MB) and when i use 0 to the DDR_SIZE, i can access to the 254MB directly (i test it using 256MB of size on ioremap functions, etc). I think is the same as 2.01 fw
When i try to send the ramin init code, it hang, but i have a little log :)
This is the line, before of enter_direct() function that i am triying:
ramin_write_dword_to_dword_offset( gpu, 0x64cb8, 0xfeed0003 );
This is the code:
Code: Select all
static void ramin_write_dword_to_dword_offset( struct gpu *gpu, uint32_t addr, uint32_t data )
{
uint32_t *fifo = gpu->fifo.virt;
uint32_t *ctrl = gpu->ctrl.virt;
uint32_t *vram = gpu->vram.virt;
uint32_t off = addr & 63;
uint32_t fifo_base;
int count=0;
{
int wptr;
int ret;
wptr =(ctrl[0x10] & (gpu->fifo.len - 1))/4;
ret = prepare_ramin_read_line256(&fifo[wptr], addr - off );
fifo_push(gpu, ret);
fprintf(fi,"Ctrl1 %x %x\n",Ctrl[0x10],Ctrl[0x11]);
fifo_wait(gpu);
fprintf(fi,"Ctrl2 %x %x\n",Ctrl[0x10],Ctrl[0x11]);
}
//wait...
usleep( 1000 );
//patch with data
vram[off] = endian( data );
//wait...
usleep( 1000 );
//copy data back
{
int wptr;
int ret;
wptr = (ctrl[0x10] & (gpu->fifo.len - 1)) / 4;
ret = prepare_ramin_write_line256(&fifo[wptr], addr - off );
fifo_push(gpu, ret);
fprintf(fi,"Ctrl3 %x %x\n",Ctrl[0x10],Ctrl[0x11]);
fifo_wait(gpu);
fprintf(fi,"Ctrl4 %x %x\n",Ctrl[0x10],Ctrl[0x11]);
}
}
And this is the log:
Start
Ctrl1 e2014ac e201448
Ctrl2 e2014ac e2014ac
Ctrl3 e201510 e2014ac
it fail on the prepare_ramin_write_line256 function (it wait fifo forever )
I have tested with differents usleep() time, and the same result.
Then, i change the prepare_ramin_read_line256() function by prepare_ramin_write_line256: the idea is to known if write access is prohibited, and i obtain:
Start
Ctrl1 e2014ac e201448
Ctrl2 e2014ac e2014ac
Ctrl3 e201510 e2014ac
So the first write work, but the second write hang.
Hypothesis: it can be a problem when blitting a large region (very short time now) or when the FIFO stops, close the door to the next packet
Greetings
