So far it appears there are two really important parts of the headers that are necessary. 1) The definitions and 2) the bit-packed structures. Nouveau has both, but I can only seem to find #1 right now, I'll post #2 as soon as I find it.
*EDIT* NOTE: This list is incomplete for all hardware. It was only the basic stuff out of nouveau_shader.h, we should include nv20_shader.h nv30_shader.h, etc. info as well. Differences are clear in the Vertex shading part. This mostly just deals with the fragment shading part.
So, without further ado, below is the general header for defining the many commands and the different command classes (jump, inst, etc.).
The header:
Code: Select all
#ifndef _SRECOMP_H
#define _SRECOMP_H
//This file contains tons of structures and stuff that
//has been ripped from Nouveau.
struct _nvs_command_set;
typedef enum {
NVS_FILE_NONE,
NVS_FILE_TEMP,
NVS_FILE_ATTRIB,
NVS_FILE_CONST,
NVS_FILE_RESULT,
NVS_FILE_ADDRESS,
NVS_FILE_UNKNOWN
} nvsRegFile;
typedef enum {
NVS_SWZ_X = 0,
NVS_SWZ_Y = 1,
NVS_SWZ_Z = 2,
NVS_SWZ_W = 3
} nvsSwzComp;
typedef struct {
nvsRegFile file;
unsigned int index;
unsigned int indexed;
unsigned int addr_reg;
nvsSwzComp addr_comp;
nvsSwzComp swizzle[4];
int negate;
int abs;
} nvsRegister;
typedef enum {
NVS_OP_UNKNOWN = 0,
NVS_OP_NOP,
NVS_OP_ABS, NVS_OP_ADD, NVS_OP_ARA, NVS_OP_ARL, NVS_OP_ARR,
NVS_OP_BRA, NVS_OP_BRK,
NVS_OP_CAL, NVS_OP_CMP, NVS_OP_COS,
NVS_OP_DDX, NVS_OP_DDY, NVS_OP_DIV, NVS_OP_DP2, NVS_OP_DP2A, NVS_OP_DP3,
NVS_OP_DP4, NVS_OP_DPH, NVS_OP_DST,
NVS_OP_EX2, NVS_OP_EXP,
NVS_OP_FLR, NVS_OP_FRC,
NVS_OP_IF,
NVS_OP_KIL,
NVS_OP_LG2, NVS_OP_LIT, NVS_OP_LOG, NVS_OP_LOOP, NVS_OP_LRP,
NVS_OP_MAD, NVS_OP_MAX, NVS_OP_MIN, NVS_OP_MOV, NVS_OP_MUL,
NVS_OP_NRM,
NVS_OP_PK2H, NVS_OP_PK2US, NVS_OP_PK4B, NVS_OP_PK4UB, NVS_OP_POW,
NVS_OP_POPA, NVS_OP_PUSHA,
NVS_OP_RCC, NVS_OP_RCP, NVS_OP_REP, NVS_OP_RET, NVS_OP_RFL, NVS_OP_RSQ,
NVS_OP_SCS, NVS_OP_SEQ, NVS_OP_SFL, NVS_OP_SGE, NVS_OP_SGT, NVS_OP_SIN,
NVS_OP_SLE, NVS_OP_SLT, NVS_OP_SNE, NVS_OP_SSG, NVS_OP_STR, NVS_OP_SUB,
NVS_OP_SWZ,
NVS_OP_TEX, NVS_OP_TXB, NVS_OP_TXD, NVS_OP_TXL, NVS_OP_TXP,
NVS_OP_UP2H, NVS_OP_UP2US, NVS_OP_UP4B, NVS_OP_UP4UB,
NVS_OP_X2D, NVS_OP_XPD,
NVS_OP_EMUL
} nvsOpcode;
typedef enum {
NVS_PREC_FLOAT32,
NVS_PREC_FLOAT16,
NVS_PREC_FIXED12,
NVS_PREC_UNKNOWN
} nvsPrecision;
typedef enum {
NVS_FR_POSITION = 0,
NVS_FR_WEIGHT = 1,
NVS_FR_NORMAL = 2,
NVS_FR_COL0 = 3,
NVS_FR_COL1 = 4,
NVS_FR_FOGCOORD = 5,
NVS_FR_TEXCOORD0 = 8,
NVS_FR_TEXCOORD1 = 9,
NVS_FR_TEXCOORD2 = 10,
NVS_FR_TEXCOORD3 = 11,
NVS_FR_TEXCOORD4 = 12,
NVS_FR_TEXCOORD5 = 13,
NVS_FR_TEXCOORD6 = 14,
NVS_FR_TEXCOORD7 = 15,
NVS_FR_BFC0 = 16,
NVS_FR_BFC1 = 17,
NVS_FR_POINTSZ = 18,
NVS_FR_FRAGDATA0 = 19,
NVS_FR_FRAGDATA1 = 20,
NVS_FR_FRAGDATA2 = 21,
NVS_FR_FRAGDATA3 = 22,
NVS_FR_CLIP0 = 23,
NVS_FR_CLIP1 = 24,
NVS_FR_CLIP2 = 25,
NVS_FR_CLIP3 = 26,
NVS_FR_CLIP4 = 27,
NVS_FR_CLIP5 = 28,
NVS_FR_CLIP6 = 29,
NVS_FR_FACING = 30,
NVS_FR_UNKNOWN
} nvsFixedReg;
typedef enum {
NVS_COND_FL, NVS_COND_LT, NVS_COND_EQ, NVS_COND_LE, NVS_COND_GT,
NVS_COND_NE, NVS_COND_GE, NVS_COND_TR, NVS_COND_UN,
NVS_COND_UNKNOWN
} nvsCond;
typedef enum {
NVS_TEX_TARGET_1D,
NVS_TEX_TARGET_2D,
NVS_TEX_TARGET_3D,
NVS_TEX_TARGET_CUBE,
NVS_TEX_TARGET_RECT,
NVS_TEX_TARGET_UNKNOWN = 0
} nvsTexTarget;
typedef enum {
NVS_SCALE_1X = 0,
NVS_SCALE_2X = 1,
NVS_SCALE_4X = 2,
NVS_SCALE_8X = 3,
NVS_SCALE_INV_2X = 5,
NVS_SCALE_INV_4X = 6,
NVS_SCALE_INV_8X = 7,
} nvsScale;
/* Arith/TEX instructions */
typedef struct nvs_instruction {
struct _nvs_command_set * header;
nvsOpcode op;
unsigned int saturate;
nvsRegister dest;
unsigned int mask;
nvsScale dest_scale;
nvsRegister src[3];
unsigned int tex_unit;
nvsTexTarget tex_target;
nvsCond cond;
nvsSwzComp cond_swizzle[4];
int cond_reg;
int cond_test;
int cond_update;
} nvsInstruction;
/* BRA, CAL, IF */
typedef struct nvs_branch {
struct _nvs_command_set * header;
nvsOpcode op;
nvsCond cond;
nvsSwzComp cond_swizzle[4];
int cond_test;
struct _nvs_command_set *target_head;
struct _nvs_command_set *target_tail;
struct _nvs_command_set *else_head;
struct _nvs_command_set *else_tail;
} nvsBranch;
/* LOOP+ENDLOOP */
typedef struct {
struct _nvs_command_set * header;
int count;
int initial;
int increment;
struct _nvs_command_set *insn_head;
struct _nvs_command_set *insn_tail;
} nvsLoop;
/* label+following instructions */
typedef struct nvs_subroutine {
struct _nvs_command_set * header;
char * label;
struct _nvs_command_set *insn_head;
struct _nvs_command_set *insn_tail;
} nvsSubroutine;
typedef struct _nvs_command_set
{
struct _nvs_command_set * parent;
struct _nvs_command_set * prev;
struct _nvs_command_set * next;
enum {
NVS_INSTRUCTION,
NVS_BRANCH,
NVS_LOOP,
NVS_SUBROUTINE
} type;
union {
nvsInstruction I;
nvsBranch B;
nvsLoop L;
nvsSubroutine S;
} data;
} nvsCommandSet;
//Now we get to the good stuff
//Compile an arbfp10 program
nvsCommandSet * AssembleShader( const char * shader );
#endif
/*
* Copyright (C) 2006 Ben Skeggs
* Copyright (C) 2007 Charles Lohr (mostly reformatting, no new content)
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
/*
* Authors:
* Ben Skeggs <darktama@iinet.net.au>
*/Code: Select all
#include "srecomp.h"
struct _opcode_info
{
const char *name;
int numsrc;
int flags;
};
#define CHECK_RANGE(idx, arr) ((idx)<sizeof(_##arr)/sizeof(const char *)) \
? _##arr[(idx)] : #arr"_OOB"
#define NODS (1<<0)
#define BRANCH_TR (1<<1)
#define BRANCH_EL (1<<2)
#define BRANCH_EN (1<<3)
#define BRANCH_RE (1<<4)
#define BRANCH_ALL (BRANCH_TR|BRANCH_EL|BRANCH_EN)
#define COUNT_INC (1<<4)
#define COUNT_IND (1<<5)
#define COUNT_NUM (1<<6)
#define COUNT_ALL (COUNT_INC|COUNT_IND|COUNT_NUM)
#define TI_UNIT (1<<7)
static struct _opcode_info ops[] = {
[NVS_OP_ABS] = {"ABS", 1, 0},
[NVS_OP_ADD] = {"ADD", 2, 0},
[NVS_OP_ARA] = {"ARA", 1, 0},
[NVS_OP_ARL] = {"ARL", 1, 0},
[NVS_OP_ARR] = {"ARR", 1, 0},
[NVS_OP_BRA] = {"BRA", 0, NODS | BRANCH_TR},
[NVS_OP_BRK] = {"BRK", 0, NODS},
[NVS_OP_CAL] = {"CAL", 0, NODS | BRANCH_TR},
[NVS_OP_CMP] = {"CMP", 2, 0},
[NVS_OP_COS] = {"COS", 1, 0},
[NVS_OP_DIV] = {"DIV", 2, 0},
[NVS_OP_DDX] = {"DDX", 1, 0},
[NVS_OP_DDY] = {"DDY", 1, 0},
[NVS_OP_DP2] = {"DP2", 2, 0},
[NVS_OP_DP2A] = {"DP2A", 3, 0},
[NVS_OP_DP3] = {"DP3", 2, 0},
[NVS_OP_DP4] = {"DP4", 2, 0},
[NVS_OP_DPH] = {"DPH", 2, 0},
[NVS_OP_DST] = {"DST", 2, 0},
[NVS_OP_EX2] = {"EX2", 1, 0},
[NVS_OP_EXP] = {"EXP", 1, 0},
[NVS_OP_FLR] = {"FLR", 1, 0},
[NVS_OP_FRC] = {"FRC", 1, 0},
[NVS_OP_IF] = {"IF", 0, NODS | BRANCH_EL | BRANCH_EN},
[NVS_OP_KIL] = {"KIL", 1, 0},
[NVS_OP_LG2] = {"LG2", 1, 0},
[NVS_OP_LIT] = {"LIT", 1, 0},
[NVS_OP_LOG] = {"LOG", 1, 0},
[NVS_OP_LOOP] = {"LOOP", 0, NODS | COUNT_ALL | BRANCH_EN},
[NVS_OP_LRP] = {"LRP", 3, 0},
[NVS_OP_MAD] = {"MAD", 3, 0},
[NVS_OP_MAX] = {"MAX", 2, 0},
[NVS_OP_MIN] = {"MIN", 2, 0},
[NVS_OP_MOV] = {"MOV", 1, 0},
[NVS_OP_MUL] = {"MUL", 2, 0},
[NVS_OP_NRM] = {"NRM", 1, 0},
[NVS_OP_PK2H] = {"PK2H", 1, 0},
[NVS_OP_PK2US] = {"PK2US", 1, 0},
[NVS_OP_PK4B] = {"PK4B", 1, 0},
[NVS_OP_PK4UB] = {"PK4UB", 1, 0},
[NVS_OP_POW] = {"POW", 2, 0},
[NVS_OP_POPA] = {"POPA", 0, 0},
[NVS_OP_PUSHA] = {"PUSHA", 1, NODS},
[NVS_OP_RCC] = {"RCC", 1, 0},
[NVS_OP_RCP] = {"RCP", 1, 0},
[NVS_OP_REP] = {"REP", 0, NODS | BRANCH_EN | COUNT_NUM},
[NVS_OP_RET] = {"RET", 0, NODS},
[NVS_OP_RFL] = {"RFL", 1, 0},
[NVS_OP_RSQ] = {"RSQ", 1, 0},
[NVS_OP_SCS] = {"SCS", 1, 0},
[NVS_OP_SEQ] = {"SEQ", 2, 0},
[NVS_OP_SFL] = {"SFL", 2, 0},
[NVS_OP_SGE] = {"SGE", 2, 0},
[NVS_OP_SGT] = {"SGT", 2, 0},
[NVS_OP_SIN] = {"SIN", 1, 0},
[NVS_OP_SLE] = {"SLE", 2, 0},
[NVS_OP_SLT] = {"SLT", 2, 0},
[NVS_OP_SNE] = {"SNE", 2, 0},
[NVS_OP_SSG] = {"SSG", 1, 0},
[NVS_OP_STR] = {"STR", 2, 0},
[NVS_OP_SUB] = {"SUB", 2, 0},
[NVS_OP_TEX] = {"TEX", 1, TI_UNIT},
[NVS_OP_TXB] = {"TXB", 1, TI_UNIT},
[NVS_OP_TXD] = {"TXD", 3, TI_UNIT},
[NVS_OP_TXL] = {"TXL", 1, TI_UNIT},
[NVS_OP_TXP] = {"TXP", 1, TI_UNIT},
[NVS_OP_UP2H] = {"UP2H", 1, 0},
[NVS_OP_UP2US] = {"UP2US", 1, 0},
[NVS_OP_UP4B] = {"UP4B", 1, 0},
[NVS_OP_UP4UB] = {"UP4UB", 1, 0},
[NVS_OP_X2D] = {"X2D", 3, 0},
[NVS_OP_XPD] = {"XPD", 2, 0},
[NVS_OP_NOP] = {"NOP", 0, NODS},
};
static struct _opcode_info *
_get_op_info(int op)
{
if (op >= (sizeof(ops) / sizeof(struct _opcode_info)))
return 0;
if (ops[op].name == 0)
return 0;
return &ops[op];
}
static const char *_SFR_STRING[] = {
[NVS_FR_POSITION] = "position",
[NVS_FR_WEIGHT] = "weight",
[NVS_FR_NORMAL] = "normal",
[NVS_FR_COL0] = "color",
[NVS_FR_COL1] = "color.secondary",
[NVS_FR_BFC0] = "bfc",
[NVS_FR_BFC1] = "bfc.secondary",
[NVS_FR_FOGCOORD] = "fogcoord",
[NVS_FR_POINTSZ] = "pointsize",
[NVS_FR_TEXCOORD0] = "texcoord[0]",
[NVS_FR_TEXCOORD1] = "texcoord[1]",
[NVS_FR_TEXCOORD2] = "texcoord[2]",
[NVS_FR_TEXCOORD3] = "texcoord[3]",
[NVS_FR_TEXCOORD4] = "texcoord[4]",
[NVS_FR_TEXCOORD5] = "texcoord[5]",
[NVS_FR_TEXCOORD6] = "texcoord[6]",
[NVS_FR_TEXCOORD7] = "texcoord[7]",
[NVS_FR_FRAGDATA0] = "data[0]",
[NVS_FR_FRAGDATA1] = "data[1]",
[NVS_FR_FRAGDATA2] = "data[2]",
[NVS_FR_FRAGDATA3] = "data[3]",
[NVS_FR_CLIP0] = "clip_plane[0]",
[NVS_FR_CLIP1] = "clip_plane[1]",
[NVS_FR_CLIP2] = "clip_plane[2]",
[NVS_FR_CLIP3] = "clip_plane[3]",
[NVS_FR_CLIP4] = "clip_plane[4]",
[NVS_FR_CLIP5] = "clip_plane[5]",
[NVS_FR_CLIP6] = "clip_plane[6]",
[NVS_FR_FACING] = "facing",
};
#define SFR_STRING(idx) CHECK_RANGE((idx), SFR_STRING)
static const char *_SWZ_STRING[] = {
[NVS_SWZ_X] = "x",
[NVS_SWZ_Y] = "y",
[NVS_SWZ_Z] = "z",
[NVS_SWZ_W] = "w"
};
#define SWZ_STRING(idx) CHECK_RANGE((idx), SWZ_STRING)
static const char *_NVS_PREC_STRING[] = {
[NVS_PREC_FLOAT32] = "R",
[NVS_PREC_FLOAT16] = "H",
[NVS_PREC_FIXED12] = "X",
[NVS_PREC_UNKNOWN] = "?"
};
#define NVS_PREC_STRING(idx) CHECK_RANGE((idx), NVS_PREC_STRING)
static const char *_NVS_COND_STRING[] = {
[NVS_COND_FL] = "FL",
[NVS_COND_LT] = "LT",
[NVS_COND_EQ] = "EQ",
[NVS_COND_LE] = "LE",
[NVS_COND_GT] = "GT",
[NVS_COND_NE] = "NE",
[NVS_COND_GE] = "GE",
[NVS_COND_TR] = "TR",
[NVS_COND_UNKNOWN] = "??"
};
nvsCommandSet * AssembleShader( const char * shader )
{
}
/*
* Copyright (C) 2006 Ben Skeggs
* Copyright (C) 2007 Charles Lohr (mostly just reformatting)
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
/*
* Authors:
* Ben Skeggs <darktama@iinet.net.au>
*/
EDIT: I guess I must be going crazy. I can't seem to find the bitwise structure. I'm starting to think I may have gotten confused when I was reading the mesa stuff and may be thinking of the brw_structs for the intel cards.
Additionally, the code that this was ripped from was http://gitweb.freedesktop.org/?p=mesa/m ... ri/nouveau
And it contains all the goodies for the end opcodes for the cards (take a look at nv40_shader.h)
Sorry all I've been able to do yet was research.
