Yes, binutils-2.16.1 still do... Didn't manage to port all the changes to 2.18.
UPD: fixed for -mpreferred-stack-boundary... sorry, took the wrong patch.
Code: Select all
diff -burN gcc-4.2.3/config.sub gcc-4.2.3-psp/config.sub
--- gcc-4.2.3/config.sub 2006-10-16 06:27:17.000000000 +0300
+++ gcc-4.2.3-psp/config.sub 2008-03-12 21:52:04.375000000 +0200
@@ -267,6 +267,7 @@
| mipsisa64sb1 | mipsisa64sb1el \
| mipsisa64sr71k | mipsisa64sr71kel \
| mipstx39 | mipstx39el \
+ | mipsallegrex | mipsallegrexel \
| mn10200 | mn10300 \
| mt \
| msp430 \
@@ -348,6 +349,7 @@
| mipsisa64sb1-* | mipsisa64sb1el-* \
| mipsisa64sr71k-* | mipsisa64sr71kel-* \
| mipstx39-* | mipstx39el-* \
+ | mipsallegrex-* | mipsallegrexel-* \
| mmix-* \
| mt-* \
| msp430-* \
@@ -690,6 +692,10 @@
basic_machine=m68k-atari
os=-mint
;;
+ psp)
+ basic_machine=mipsallegrexel-psp
+ os=-elf
+ ;;
mips3*-*)
basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
;;
diff -burN gcc-4.2.3/gcc/c-incpath.c gcc-4.2.3-psp/gcc/c-incpath.c
--- gcc-4.2.3/gcc/c-incpath.c 2007-09-01 18:28:30.000000000 +0300
+++ gcc-4.2.3-psp/gcc/c-incpath.c 2008-03-12 21:52:04.375000000 +0200
@@ -340,13 +340,18 @@
cpp_dir *p;
#if defined (HAVE_DOS_BASED_FILE_SYSTEM)
- /* Convert all backslashes to slashes. The native CRT stat()
- function does not recognize a directory that ends in a backslash
- (unless it is a drive root dir, such "c:\"). Forward slashes,
- trailing or otherwise, cause no problems for stat(). */
- char* c;
- for (c = path; *c; c++)
- if (*c == '\\') *c = '/';
+ /* Remove unnecessary trailing slashes. On some versions of MS
+ Windows, trailing _forward_ slashes cause no problems for stat().
+ On newer versions, stat() does not recognise a directory that ends
+ in a '\\' or '/', unless it is a drive root dir, such as "c:/",
+ where it is obligatory. */
+ int pathlen = strlen (path);
+ char* end = path + pathlen - 1;
+ /* Preserve the lead '/' or lead "c:/". */
+ char* start = path + (pathlen > 2 && path[1] == ':' ? 3 : 1);
+
+ for (; end > start && IS_DIR_SEPARATOR (*end); end--)
+ *end = 0;
#endif
p = XNEW (cpp_dir);
diff -burN gcc-4.2.3/gcc/config/mips/allegrex.md gcc-4.2.3-psp/gcc/config/mips/allegrex.md
--- gcc-4.2.3/gcc/config/mips/allegrex.md 1970-01-01 02:00:00.000000000 +0200
+++ gcc-4.2.3-psp/gcc/config/mips/allegrex.md 2008-03-12 21:52:04.390625000 +0200
@@ -0,0 +1,183 @@
+;; Sony ALLEGREX instructions.
+;; Copyright (C) 2005 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+; Multiply Add and Subtract.
+
+(define_insn "allegrex_madd"
+ [(set (match_operand:SI 0 "register_operand" "+l")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))
+ (match_dup 0)))
+ (clobber (match_scratch:SI 3 "=h"))]
+ "TARGET_ALLEGREX"
+ "madd\t%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_msub"
+ [(set (match_operand:SI 0 "register_operand" "+l")
+ (minus:SI (match_dup 0)
+ (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))))
+ (clobber (match_scratch:SI 3 "=h"))]
+ "TARGET_ALLEGREX"
+ "msub\t%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+
+; Min and max.
+
+(define_insn "sminsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (smin:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_ALLEGREX"
+ "min\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "smaxsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (smax:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_ALLEGREX"
+ "max\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+
+; Extended shift instructions.
+
+(define_insn "allegrex_bitrev"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_BITREV))]
+ "TARGET_ALLEGREX"
+ "bitrev\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_wsbh"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_WSBH))]
+ "TARGET_ALLEGREX"
+ "wsbh\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_wsbw"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_WSBW))]
+ "TARGET_ALLEGREX"
+ "wsbw\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+
+; Count leading ones, count trailing zeros, and count trailing ones (clz is
+; already defined).
+
+(define_insn "allegrex_clo"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_CLO))]
+ "TARGET_ALLEGREX"
+ "clo\t%0,%1"
+ [(set_attr "type" "clz")
+ (set_attr "mode" "SI")])
+
+(define_expand "ctzsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (ctz:SI (match_operand:SI 1 "register_operand")))]
+ "TARGET_ALLEGREX"
+{
+ rtx r1;
+
+ r1 = gen_reg_rtx (SImode);
+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+ emit_insn (gen_clzsi2 (operands[0], r1));
+ DONE;
+})
+
+(define_expand "allegrex_cto"
+ [(set (match_operand:SI 0 "register_operand")
+ (unspec:SI [(match_operand:SI 1 "register_operand")]
+ UNSPEC_CTO))]
+ "TARGET_ALLEGREX"
+{
+ rtx r1;
+
+ r1 = gen_reg_rtx (SImode);
+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+ emit_insn (gen_allegrex_clo (operands[0], r1));
+ DONE;
+})
+
+
+; Misc.
+
+(define_insn "allegrex_sync"
+ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
+ "TARGET_ALLEGREX"
+ "sync"
+ [(set_attr "type" "unknown")
+ (set_attr "mode" "none")])
+
+(define_insn "allegrex_cache"
+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
+ (match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_CACHE)]
+ "TARGET_ALLEGREX"
+ "cache\t%0,0(%1)"
+ [(set_attr "type" "unknown")
+ (set_attr "mode" "none")])
+
+
+; Floating-point builtins.
+
+(define_insn "allegrex_ceil_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_CEIL_W_S))]
+ "TARGET_ALLEGREX"
+ "ceil.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
+
+(define_insn "allegrex_floor_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_FLOOR_W_S))]
+ "TARGET_ALLEGREX"
+ "floor.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
+
+(define_insn "allegrex_round_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_ROUND_W_S))]
+ "TARGET_ALLEGREX"
+ "round.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
diff -burN gcc-4.2.3/gcc/config/mips/mips.c gcc-4.2.3-psp/gcc/config/mips/mips.c
--- gcc-4.2.3/gcc/config/mips/mips.c 2007-10-24 20:54:40.000000000 +0300
+++ gcc-4.2.3-psp/gcc/config/mips/mips.c 2008-03-12 21:57:54.812500000 +0200
@@ -179,6 +179,12 @@
MIPS_VOID_FTYPE_V2HI_V2HI,
MIPS_VOID_FTYPE_V4QI_V4QI,
+ /* For the Sony ALLEGREX. */
+ MIPS_SI_FTYPE_QI,
+ MIPS_SI_FTYPE_HI,
+ MIPS_VOID_FTYPE_VOID,
+ MIPS_SI_FTYPE_SF,
+
/* The last type. */
MIPS_MAX_FTYPE_MAX
};
@@ -220,6 +226,11 @@
/* As above, but the instruction only sets a single $fcc register. */
MIPS_BUILTIN_CMP_SINGLE,
+ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
+ is the function code (must be less than 32) and operand 1 is the base
+ address. */
+ MIPS_BUILTIN_CACHE,
+
/* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
MIPS_BUILTIN_BPOSGE32
};
@@ -404,6 +415,7 @@
static rtx mips_expand_builtin_compare (enum mips_builtin_type,
enum insn_code, enum mips_fp_condition,
rtx, tree);
+static rtx mips_expand_builtin_cache (enum insn_code icode, rtx, tree);
static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
static void mips_encode_section_info (tree, rtx, int);
static void mips_extra_live_on_entry (bitmap);
@@ -601,6 +613,10 @@
should arrange to call mips32 hard floating point code. */
int mips16_hard_float;
+/* Preferred stack boundary for proper stack vars alignment */
+unsigned int mips_preferred_stack_boundary;
+unsigned int mips_preferred_stack_align;
+
/* The architecture selected by -mipsN. */
static const struct mips_cpu_info *mips_isa_info;
@@ -719,6 +735,7 @@
/* MIPS II */
{ "r6000", PROCESSOR_R6000, 2 },
+ { "allegrex", PROCESSOR_ALLEGREX, 2 },
/* MIPS III */
{ "r4000", PROCESSOR_R4000, 3 },
@@ -5187,6 +5204,22 @@
mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
}
+ /* Validate -mpreferred-stack-boundary= value, or provide default.
+ The default of 128-bit is for newABI else 64-bit. */
+ mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
+ mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
+ if (mips_preferred_stack_boundary_string)
+ {
+ i = atoi (mips_preferred_stack_boundary_string);
+ if (i < 2 || i > 12)
+ error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
+ else
+ {
+ mips_preferred_stack_align = (1 << i);
+ mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
+ }
+ }
+
/* Thread-local relocation operators. */
mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
@@ -10446,6 +10479,67 @@
BPOSGE_BUILTIN (32, MASK_DSP)
};
+/* Builtin functions for the Sony ALLEGREX processor.
+
+ These have the `__builtin_allgrex_' prefix instead of `__builtin_mips_'
+ to maintain compatibility with Sony's ALLEGREX GCC port.
+
+ Some of the builtins may seem redundant, but they are the same as the
+ builtins defined in the Sony compiler. I chose to map redundant and
+ trivial builtins to the original instruction instead of creating
+ duplicate patterns specifically for the ALLEGREX (as Sony does). */
+
+/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
+ FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Same as the above, but mapped to an instruction that doesn't share the
+ NAME. NAME is the name of the builtin without the builtin prefix. */
+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_ ## INSN, 0, "__builtin_allegrex_" #NAME, \
+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
+ CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
+ builtin_description fields. */
+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Define a builtin with a specific function TYPE. */
+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, TARGET_FLAGS }
+
+static const struct builtin_description allegrex_bdesc[] =
+{
+ DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(wsbw, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
+ SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0)
+};
+
/* This helps provide a mapping from builtin function codes to bdesc
arrays. */
@@ -10466,6 +10560,7 @@
{
{ mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
{ sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
+ { allegrex_bdesc, ARRAY_SIZE (allegrex_bdesc), PROCESSOR_ALLEGREX },
{ dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
};
@@ -10569,6 +10664,9 @@
case MIPS_BUILTIN_BPOSGE32:
return mips_expand_builtin_bposge (type, target);
+ case MIPS_BUILTIN_CACHE:
+ return mips_expand_builtin_cache (icode, target, arglist);
+
default:
return 0;
}
@@ -10587,8 +10685,8 @@
tree V4QI_type_node;
unsigned int offset;
- /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
- if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
+ /* We have only builtins for -mpaired-single, -mips3d and -mdsp and the Sony ALLEGREX. */
+ if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP && !TARGET_ALLEGREX)
return;
if (TARGET_PAIRED_SINGLE_FLOAT)
@@ -10653,6 +10751,44 @@
double_type_node, double_type_node, NULL_TREE);
}
+ if (TARGET_ALLEGREX)
+ {
+ types[MIPS_SI_FTYPE_QI]
+ = build_function_type_list (intSI_type_node,
+ intQI_type_node,
+ NULL_TREE);
+
+ types[MIPS_SI_FTYPE_HI]
+ = build_function_type_list (intSI_type_node,
+ intHI_type_node,
+ NULL_TREE);
+
+ types[MIPS_SI_FTYPE_SI]
+ = build_function_type_list (intSI_type_node,
+ intSI_type_node,
+ NULL_TREE);
+
+ types[MIPS_SI_FTYPE_SI_SI]
+ = build_function_type_list (intSI_type_node,
+ intSI_type_node, intSI_type_node,
+ NULL_TREE);
+
+ types[MIPS_VOID_FTYPE_VOID]
+ = build_function_type_list (void_type_node, void_type_node, NULL_TREE);
+
+ types[MIPS_VOID_FTYPE_SI_SI]
+ = build_function_type_list (void_type_node,
+ intSI_type_node, intSI_type_node, NULL_TREE);
+
+ types[MIPS_SF_FTYPE_SF]
+ = build_function_type_list (float_type_node,
+ float_type_node, NULL_TREE);
+
+ types[MIPS_SI_FTYPE_SF]
+ = build_function_type_list (intSI_type_node,
+ float_type_node, NULL_TREE);
+ }
+
if (TARGET_DSP)
{
V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
@@ -10834,6 +10970,10 @@
switch (i)
{
+ case 0:
+ emit_insn (GEN_FCN (icode) (0));
+ break;
+
case 2:
emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
break;
@@ -11035,4 +11175,28 @@
return UNKNOWN;
}
+
+/* Expand a __builtin_allegrex_cache() function. Make sure the passed
+ cache function code is less than 32. */
+
+static rtx
+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree arglist)
+{
+ rtx op0, op1;
+
+ op0 = mips_prepare_builtin_arg (icode, 0, &arglist);
+ op1 = mips_prepare_builtin_arg (icode, 1, &arglist);
+
+ if (GET_CODE (op0) == CONST_INT)
+ if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f)
+ {
+ error ("invalid function code '%d'", INTVAL (op0));
+ return const0_rtx;
+ }
+
+ emit_insn (GEN_FCN (icode) (op0, op1));
+ return target;
+}
+
+
#include "gt-mips.h"
diff -burN gcc-4.2.3/gcc/config/mips/mips.h gcc-4.2.3-psp/gcc/config/mips/mips.h
--- gcc-4.2.3/gcc/config/mips/mips.h 2007-09-01 18:28:30.000000000 +0300
+++ gcc-4.2.3-psp/gcc/config/mips/mips.h 2008-03-12 22:02:23.937500000 +0200
@@ -59,6 +59,7 @@
PROCESSOR_SB1,
PROCESSOR_SB1A,
PROCESSOR_SR71000,
+ PROCESSOR_ALLEGREX,
PROCESSOR_MAX
};
@@ -211,6 +212,7 @@
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
|| mips_arch == PROCESSOR_SB1A)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
+#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
/* Scheduling target defines. */
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
@@ -226,6 +228,7 @@
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
|| mips_tune == PROCESSOR_SB1A)
+#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
/* True if the pre-reload scheduler should try to create chains of
multiply-add or multiply-subtract instructions. For example,
@@ -598,6 +601,9 @@
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
+/* ISA has just the integer condition move instructions (movn,movz) */
+#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
+
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (ISA_MIPS4 \
@@ -614,7 +620,8 @@
/* ISA has conditional trap instructions. */
#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
- && !TARGET_MIPS16)
+ && !TARGET_MIPS16 \
+ && !TARGET_ALLEGREX)
/* ISA has integer multiply-accumulate instructions, madd and msub. */
#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
@@ -632,6 +639,7 @@
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
+ || TARGET_ALLEGREX \
) && !TARGET_MIPS16)
/* ISA has double-word count leading zeroes/ones instruction (not
@@ -679,6 +687,7 @@
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
+ || TARGET_ALLEGREX \
))
/* ISA has 64-bit rotate right instruction. */
@@ -712,11 +721,13 @@
/* ISA includes the MIPS32r2 seb and seh instructions. */
#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
+ || TARGET_ALLEGREX \
))
/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
+ || TARGET_ALLEGREX \
))
/* True if the result of a load is not available to the next instruction.
@@ -747,7 +758,8 @@
#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
- || TARGET_MIPS5500)
+ || TARGET_MIPS5500 \
+ || TARGET_ALLEGREX)
/* Add -G xx support. */
@@ -1816,7 +1828,7 @@
`current_function_outgoing_args_size'. */
#define OUTGOING_REG_PARM_STACK_SPACE
-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
+#define STACK_BOUNDARY (mips_preferred_stack_boundary)
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
@@ -1972,7 +1984,7 @@
/* Treat LOC as a byte offset from the stack pointer and round it up
to the next fully-aligned offset. */
#define MIPS_STACK_ALIGN(LOC) \
- (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
+ ((LOC) + (mips_preferred_stack_align - 1) & -(mips_preferred_stack_align))
/* Implement `va_start' for varargs and stdarg. */
@@ -2705,6 +2717,10 @@
#endif
#endif
+extern unsigned int mips_preferred_stack_boundary;
+extern unsigned int mips_preferred_stack_align;
+extern const char *mips_preferred_stack_boundary_string;
+
#ifndef HAVE_AS_TLS
#define HAVE_AS_TLS 0
#endif
diff -burN gcc-4.2.3/gcc/config/mips/mips.md gcc-4.2.3-psp/gcc/config/mips/mips.md
--- gcc-4.2.3/gcc/config/mips/mips.md 2007-10-22 23:09:07.000000000 +0300
+++ gcc-4.2.3-psp/gcc/config/mips/mips.md 2008-03-12 21:52:04.390625000 +0200
@@ -144,6 +144,21 @@
(UNSPEC_MTHLIP 365)
(UNSPEC_WRDSP 366)
(UNSPEC_RDDSP 367)
+
+ ;; Sony ALLEGREX instructions
+ (UNSPEC_WSBH 401)
+ (UNSPEC_WSBW 402)
+
+ (UNSPEC_CLO 403)
+ (UNSPEC_CTO 404)
+
+ (UNSPEC_CACHE 405)
+ (UNSPEC_SYNC 406)
+
+ (UNSPEC_CEIL_W_S 407)
+ (UNSPEC_FLOOR_W_S 408)
+ (UNSPEC_ROUND_W_S 409)
+
]
)
@@ -1616,9 +1631,9 @@
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
- "!TARGET_64BIT && ISA_HAS_MSAC"
+ "!TARGET_64BIT && (ISA_HAS_MSAC || TARGET_ALLEGREX)"
{
- if (TARGET_MIPS5500)
+ if (TARGET_MIPS5500 || TARGET_ALLEGREX)
return "msub<u>\t%1,%2";
else
return "msac<u>\t$0,%1,%2";
@@ -1733,12 +1748,12 @@
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(match_operand:DI 3 "register_operand" "0")))]
- "(TARGET_MAD || ISA_HAS_MACC)
+ "(TARGET_MAD || ISA_HAS_MACC || TARGET_ALLEGREX)
&& !TARGET_64BIT"
{
if (TARGET_MAD)
return "mad<u>\t%1,%2";
- else if (TARGET_MIPS5500)
+ else if (TARGET_MIPS5500 || TARGET_ALLEGREX)
return "madd<u>\t%1,%2";
else
/* See comment in *macc. */
@@ -2018,6 +2033,32 @@
;;
;; ....................
;;
+;; FIND FIRST BIT INSTRUCTION
+;;
+;; ....................
+;;
+
+(define_expand "ffs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
+ "ISA_HAS_CLZ_CLO"
+{
+ rtx r1, r2, r3, r4;
+
+ r1 = gen_reg_rtx (<MODE>mode);
+ r2 = gen_reg_rtx (<MODE>mode);
+ r3 = gen_reg_rtx (<MODE>mode);
+ r4 = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_neg<mode>2 (r1, operands[1]));
+ emit_insn (gen_and<mode>3 (r2, operands[1], r1));
+ emit_insn (gen_clz<mode>2 (r3, r2));
+ emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
+ emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
+ DONE;
+})
+;;
+;; ....................
+;;
;; NEGATION and ONE'S COMPLEMENT
;;
;; ....................
@@ -4280,6 +4321,25 @@
[(set_attr "type" "shift")
(set_attr "mode" "<MODE>")])
+(define_expand "rotl<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (rotate:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "ISA_HAS_ROTR_<MODE>"
+{
+ rtx temp;
+
+ if (GET_CODE (operands[2]) == CONST_INT)
+ temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
+ else
+ {
+ temp = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_neg<mode>2 (temp, operands[2]));
+ }
+ emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
+ DONE;
+})
+
;;
;; ....................
;;
@@ -5370,7 +5430,7 @@
(const_int 0)])
(match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
(match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"@
mov%T4\t%0,%z2,%1
mov%t4\t%0,%z3,%1"
@@ -5400,8 +5460,12 @@
(if_then_else:GPR (match_dup 5)
(match_operand:GPR 2 "reg_or_0_operand")
(match_operand:GPR 3 "reg_or_0_operand")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
{
+ if (ISA_HAS_INT_CONDMOVE
+ && GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_FLOAT)
+ FAIL;
+
gen_conditional_move (operands);
DONE;
})
@@ -5495,3 +5559,6 @@
; The MIPS DSP Instructions.
(include "mips-dsp.md")
+
+; Sony ALLEGREX instructions.
+(include "allegrex.md")
diff -burN gcc-4.2.3/gcc/config/mips/mips.opt gcc-4.2.3-psp/gcc/config/mips/mips.opt
--- gcc-4.2.3/gcc/config/mips/mips.opt 2007-09-01 18:28:30.000000000 +0300
+++ gcc-4.2.3-psp/gcc/config/mips/mips.opt 2008-03-12 22:03:21.453125000 +0200
@@ -219,3 +219,7 @@
mxgot
Target Report Var(TARGET_XGOT)
Lift restrictions on GOT size
+
+mpreferred-stack-boundary=
+Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
+Attempt to keep stack aligned to this power of 2
diff -burN gcc-4.2.3/gcc/config/mips/psp.h gcc-4.2.3-psp/gcc/config/mips/psp.h
--- gcc-4.2.3/gcc/config/mips/psp.h 1970-01-01 02:00:00.000000000 +0200
+++ gcc-4.2.3-psp/gcc/config/mips/psp.h 2008-03-12 21:52:04.406250000 +0200
@@ -0,0 +1,31 @@
+/* Support for Sony's Playstation Portable (PSP).
+ Copyright (C) 2005 Free Software Foundation, Inc.
+ Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+/* Override the startfile spec to include crt0.o. */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
+
+/* Get rid of the .pdr section. */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "-mno-pdr"
diff -burN gcc-4.2.3/gcc/config/mips/t-allegrex gcc-4.2.3-psp/gcc/config/mips/t-allegrex
--- gcc-4.2.3/gcc/config/mips/t-allegrex 1970-01-01 02:00:00.000000000 +0200
+++ gcc-4.2.3-psp/gcc/config/mips/t-allegrex 2008-03-12 21:52:04.406250000 +0200
@@ -0,0 +1,29 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS =
+MULTILIB_DIRNAMES =
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
diff -burN gcc-4.2.3/gcc/config.gcc gcc-4.2.3-psp/gcc/config.gcc
--- gcc-4.2.3/gcc/config.gcc 2007-12-27 11:45:20.000000000 +0200
+++ gcc-4.2.3-psp/gcc/config.gcc 2008-03-12 21:52:04.406250000 +0200
@@ -1652,6 +1652,18 @@
tmake_file=mips/t-r3900
use_fixproto=yes
;;
+mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
+ tm_file="elfos.h ${tm_file} mips/elf.h"
+ tmake_file=mips/t-allegrex
+ target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
+ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
+ case ${target} in
+ mipsallegrex*-psp-elf*)
+ tm_file="${tm_file} mips/psp.h"
+ ;;
+ esac
+ use_fixproto=yes
+ ;;
mmix-knuth-mmixware)
need_64bit_hwint=yes
;;
diff -burN gcc-4.2.3/gcc/version.c gcc-4.2.3-psp/gcc/version.c
--- gcc-4.2.3/gcc/version.c 2005-03-16 08:04:10.000000000 +0200
+++ gcc-4.2.3-psp/gcc/version.c 2008-03-12 21:52:04.406250000 +0200
@@ -8,7 +8,7 @@
in parentheses. You may also wish to include a number indicating
the revision of your modified compiler. */
-#define VERSUFFIX ""
+#define VERSUFFIX " (PSPDEV 20080312-gauri)"
/* This is the location of the online document giving instructions for
reporting bugs. If you distribute a modified version of GCC,
@@ -17,7 +17,7 @@
forward us bugs reported to you, if you determine that they are
not bugs in your modifications.) */
-const char bug_report_url[] = "<URL:http://gcc.gnu.org/bugs.html>";
+const char bug_report_url[] = "<URL:http://wiki.pspdev.org/psp:toolchain#bugs>";
/* The complete version string, assembled from several pieces.
BASEVER, DATESTAMP, and DEVPHASE are defined by the Makefile. */